OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 417

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
25.5.3.4 Application Interrupt and Reset Control Register
Table 384. ICSR bit assignments
[1]
When you write to the ICSR, the effect is Unpredictable if you:
The AIRCR provides endian status for data accesses and reset control of the system. See
the register summary in
To write to this register, you must write 0x05FA to the VECTKEY field, otherwise the
processor ignores the write.
The bit assignments are:
Table 385. AIRCR bit assignments
Bits
[22]
[21:18]
[17:12]
[11:6]
[5:0]
Bits
[31:16]
[15]
[14:3]
•
•
This is the same value as IPSR bits[5:0], see
write 1 to the PENDSVSET bit and write 1 to the PENDSVCLR bit
write 1 to the PENDSTSET bit and write 1 to the PENDSTCLR bit.
Name
ISRPENDING
-
VECTPENDING
-
VECTACTIVE
Read: Reserved
Write: VECTKEY
ENDIANESS
-
Name
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
[1]
Table 25–382
Type
RO
-
RO
-
RO
Type
RW
RO
-
Indicates the exception number of the highest priority
Reserved.
Function
Interrupt pending flag, excluding NMI and Faults:
0 = interrupt not pending
1 = interrupt pending.
Reserved.
pending enabled exception:
0 = no pending exceptions
Nonzero = the exception number of the highest priority
pending enabled exception.
Contains the active exception number:
0 = Thread mode
Nonzero = The exception number
active exception.
Remark: Subtract 16 from this value to obtain the
CMSIS IRQ number that identifies the corresponding bit
in the Interrupt Clear-Enable, Set-Enable,
Clear-Pending, Set-pending, and Priority Register, see
Table
Chapter 25: LPC122x Appendix ARM Cortex-M0
and
Function
Register key:
Reads as Unknown
On writes, write 0x05FA to VECTKEY, otherwise the
write is ignored.
Data endianness implemented:
0 = Little-endian
1 = Big-endian.
Reserved
Table
25–356.
Table 25–385
25–356.
for its attributes.
[1]
UM10441
of the currently
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