OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 298

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
19.6.3 A/D Interrupt Enable Register
19.6.4 A/D Data Registers
Table 279. A/D Global Data Register (GDR - address 0x4002 0004) bit description
This register allows control over which A/D channels generate an interrupt when a
conversion is complete. For example, it may be desirable to use some A/D channels to
monitor sensors by continuously performing conversions on them. The most recent
results are read by the application program whenever they are needed. In this case, an
interrupt is not desirable at the end of each conversion for some A/D channels.
Table 280. A/D Interrupt Enable Register (INTEN - address 0x4002 000C) bit description
The A/D Data Register hold the result when an A/D conversion is complete, and also
include the flags that indicate when a conversion has been completed and when a
conversion overrun has occurred.
Bit
5:0
15:6
23:16 -
26:24 CHN
29:27 -
30
31
Bit
7:0
8
31:9 -
Symbol
ADINTEN
ADGINTEN
Symbol
-
RESULT
OVERRUN
DONE
All information provided in this document is subject to legal disclaimers.
Description
Reserved. These bits always read as zeros.
When DONE is 1, this field contains a binary fraction representing
the voltage on the ADn pin selected by the SEL field, divided by the
voltage on the V
the voltage on the ADn pin was less than, equal to, or close to that
on V
equal to, or greater than that on V
Reserved. These bits always read as zeros.
These bits contain the channel from which the RESULT bits were
converted.
Reserved. These bits always read as zeros.
This bit is 1 in burst mode if the results of one or more conversions
was (were) lost and overwritten before the conversion that produced
the result in the RESULT bits.
This bit is set to 1 when an A/D conversion completes. It is cleared
when this register is read and when the ADCR is written. If the
ADCR is written while a conversion is still in progress, this bit is set
and a new conversion is started.
Description
These bits allow control over which A/D channels generate
interrupts for conversion completion. When bit 0 is one, completion
of a conversion on A/D channel 0 will generate an interrupt, when bit
1 is one, completion of a conversion on A/D channel 1 will generate
an interrupt, etc.
When 1, enables the global DONE flag in ADDR to generate an
interrupt. When 0, only the individual A/D channels enabled by
ADINTEN 7:0 will generate interrupts.
Reserved. These bits always read as zeros.
Rev. 1 — 15 February 2011
SS
, while 0x3FF indicates that the voltage on ADn was close to,
DD(3V3)
pin: V/V
REF
REF
. Zero in the field indicates that
.
Chapter 19: LPC122x ADC
UM10441
© NXP B.V. 2011. All rights reserved.
298 of 442
Reset
value
0
X
0
X
0
0
0
Reset
value
0x00
1
0