OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 143

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
9.5.6.1.1 UART receiver DMA
9.5.6.1.2 UART transmitter DMA
9.5.7 UART Line Control Register
9.5.8 UART Modem Control Register
In DMA mode, the receiver DMA request is asserted when the receiver FIFO level is equal
to or greater than trigger level, or if a character time-out occurs. See the description of the
RX Trigger Level above. The receiver DMA request is cleared by the DMA controller.
In DMA mode, the transmitter DMA request is asserted when the transmitter FIFO
transitions to not full. The transmitter DMA request is cleared by the DMA controller.
The LCR determines the format of the data character that is to be transmitted or received.
Table 146. UART Line Control Register (LCR - address 0x4000 800C) bit description
The MCR enables the modem loopback mode and controls the modem output signals.
Bit
1:0
2
3
5:4
6
7
31:
8
Symbol Value Description
WLS
SBS
PE
PST
BC
DLAB
-
0x0
0x1
0x2
0x3
0
1
0
1
0x0
0x1
0x2
0x3
0
1
0
1
-
All information provided in this document is subject to legal disclaimers.
Word Length Select
5-bit character length.
6-bit character length.
7-bit character length.
8-bit character length.
Stop Bit Select
1 stop bit.
2 stop bits (1.5 if LCR[1:0]=00).
Parity Enable
Disable parity generation and checking.
Enable parity generation and checking.
Parity Select
Odd parity. Number of 1s in the transmitted character and the
attached parity bit will be odd.
Even Parity. Number of 1s in the transmitted character and the
attached parity bit will be even.
Forced 1 stick parity.
Forced 0 stick parity.
Break Control
Disable break transmission.
Enable break transmission. Output pin UART TXD is forced to logic
0 when LCR[6] is active high.
Divisor Latch Access Bit (DLAB)
Disable access to Divisor Latches.
Enable access to Divisor Latches.
Reserved
Rev. 1 — 15 February 2011
Chapter 9: LPC122x UART0 with modem control
UM10441
© NXP B.V. 2011. All rights reserved.
143 of 442
Reset
value
0
0
0
0
0
0
-