OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 181
OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
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NXP Semiconductors
UM10441
User manual
11.5.1 I
The I
master receiver mode, slave transmitter mode and slave receiver mode.
The I
power off to the ARM Cortex-M0 without interfering with other devices on the same
I
Fast-Mode Plus supports a 1 Mbit/sec transfer rate to communicate with the I
which NXP Semiconductors is now providing.
In order to use Fast-Mode Plus, the I
IOCONFIG register block, see
400 kHz and up to 1 MHz may be selected, see
2
2
Fig 13. I
•
C-bus.
C Fast-mode Plus
Data transfer from a slave transmitter to a master receiver. The first byte (the slave
address) is transmitted by the master. The slave then returns an acknowledge bit.
Next follows the data bytes transmitted by the slave to the master. The master returns
an acknowledge bit after all received bytes other than the last byte. At the end of the
last received byte, a “not acknowledge” is returned. The master device generates all
of the serial clock pulses and the START and STOP conditions. A transfer is ended
with a STOP condition or with a Repeated START condition. Since a Repeated
START condition is also the beginning of the next serial transfer, the I
be released.
2
2
C interface is byte oriented and has four operating modes: master transmitter mode,
C interface complies with the entire I
I
2
C bus
2
C-bus configuration
SDA
All information provided in this document is subject to legal disclaimers.
LPC122x
Rev. 1 — 15 February 2011
SCL
Table 96
pull-up
resistor
OTHER DEVICE WITH
2
C pins must be properly configured in the
I
2
C INTERFACE
and
2
C specification, supporting the ability to turn
Table
Chapter 11: LPC122x I2C-bus controller
Table
pull-up
resistor
97. In Fast-mode Plus, rates above
188.
OTHER DEVICE WITH
I
2
C INTERFACE
UM10441
© NXP B.V. 2011. All rights reserved.
2
C bus will not
2
SDA
SCL
C products
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