OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 142

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
9.5.6.1 DMA Operation
9.5.6 UART FIFO Control Register
the last THRE = 1 event. This delay is provided to give the CPU time to write data to THR
without a THRE interrupt to decode and service. A THRE interrupt is set immediately if the
UART THR FIFO has held two or more characters at one time and currently, the THR is
empty. The THRE interrupt is reset when a THR write occurs or a read of the IIR occurs
and the THRE is the highest interrupt (IIR[3:1] = 001).
The FCR controls the operation of the UART RX and TX FIFOs.
Table 145. UART FIFO Control Register (FCR - address 0x4000 8008, Write Only) bit
The user can optionally operate the UART transmit and/or receive using the micro DMA.
The DMA mode is determined by the DMA Mode Select bit in the FCR register. This bit
only has an effect when the FIFOs are enabled via the FIFO Enable bit in the FCR
register.
Bit
0
1
2
3
5:4
7:6
31:8 -
Symbol
FIFOEN
RXFIFO
RS
TXFIFO
RS
DMAMO
DE
-
RXTL
description
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
0
1
0
1
0x0
-
0x1
0x2
0x3
Rev. 1 — 15 February 2011
FIFO Enable
UART FIFOs are disabled. Must not be used in the application.
Active high enable for both UART RX and TX FIFOs and FCR[7:1]
access. This bit must be set for proper UART operation. Any
transition on this bit will automatically clear the UART FIFOs.
RX FIFO Reset
No impact on either of UART FIFOs.
Writing a logic 1 to FCR[1] will clear all bytes in UART RX FIFO,
reset the pointer logic. This bit is self-clearing.
TX FIFO Reset
No impact on either of UART FIFOs.
Writing a logic 1 to FCR[2] will clear all bytes in UART TX FIFO,
reset the pointer logic. This bit is self-clearing.
DMA Mode Select. When the FIFO enable bit (bit 0 of this
register) is set, this bit selects the DMA mode. See
Section
DMA not used.
DMA mode enabled.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
RX Trigger Level. These two bits determine how many receiver
UART FIFO characters must be written before an interrupt is
activated.
Trigger level 0 (1 character or 0x01).
Trigger level 1 (4 characters or 0x04).
Trigger level 2 (8 characters or 0x08).
Trigger level 3 (14 characters or 0x0E).
Reserved
9.5.6.1.
Chapter 9: LPC122x UART0 with modem control
UM10441
© NXP B.V. 2011. All rights reserved.
142 of 442
Reset
value
0
0
0
0
NA
0
-