OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 235

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
12.7.2.5 SPI format with CPOL = 1,CPHA = 1
12.7.3 Semiconductor Microwire frame format
The transfer signal sequence for SPI format with CPOL = 1, CPHA = 1 is shown in
Figure
In this configuration, during idle periods:
If the SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SSEL master signal being driven LOW. Master’s MOSI is
enabled. After a further one half SCK period, both master and slave data are enabled onto
their respective transmission lines. At the same time, the SCK is enabled with a falling
edge transition. Data is then captured on the rising edges and propagated on the falling
edges of the SCK signal.
After all bits have been transferred, in the case of a single word transmission, the SSEL
line is returned to its idle HIGH state one SCK period after the last bit has been captured.
For continuous back-to-back transmissions, the SSEL pins remains in its active LOW
state, until the final bit of the last word has been captured, and then returns to its idle state
as described above. In general, for continuous back-to-back transfers the SSEL pin is
held LOW between successive data words and termination is the same as that of the
single word transfer.
Figure 34
format when back-to-back frames are transmitted.
Fig 33. SPI Frame Format with CPOL = 1 and CPHA = 1
•
•
•
The CLK signal is forced HIGH.
SSEL is forced HIGH.
The transmit MOSI/MISO pad is in high impedance.
33, which covers both single and continuous transfers.
shows the Microwire frame format for a single frame.
All information provided in this document is subject to legal disclaimers.
SSEL
MOSI
MISO
SCK
Rev. 1 — 15 February 2011
Q
MSB
MSB
4 to 16 bit
Chapter 12: LPC122x SSP controller
LSB
LSB
Figure 35
Q
UM10441
© NXP B.V. 2011. All rights reserved.
shows the same
235 of 442