OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 407
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OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
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NXP Semiconductors
UM10441
User manual
25.4.7.10.1 Syntax
25.4.7.10.2 Operation
25.4.7.10.3 Restrictions
25.4.7.10.4 Condition flags
25.4.7.10.5 Examples
25.4.7.11.1 Syntax
25.4.7.11.2 Operation
25.4.7.10 SVC
25.4.7.11 WFE
25.4.7.9.3 Restrictions
25.4.7.9.4 Condition flags
25.4.7.9.5 Examples
See also
There are no restrictions.
This instruction does not change the flags.
Supervisor Call.
SVC #imm
where:
The SVC instruction causes the SVC exception.
imm is ignored by the processor. If required, it can be retrieved by the exception handler to
determine what service is being requested.
There are no restrictions.
This instruction does not change the flags.
Wait For Event.
Remark: The WFE instruction is not implemented on the LPCIdesit.
WFE
If the event register is 0, WFE suspends execution until one of the following events
occurs:
imm is an integer in the range 0-255.
SEV ; Send Event
SVC #0x32 ; Supervisor Call (SVC handler can extract the immediate value
Section
All information provided in this document is subject to legal disclaimers.
25–25.4.7.11.
; by locating it via the stacked PC)
Rev. 1 — 15 February 2011
Chapter 25: LPC122x Appendix ARM Cortex-M0
UM10441
© NXP B.V. 2011. All rights reserved.
407 of 442
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