OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 394

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
25.4.5.2.2 Operation
25.4.5.2.3 Restrictions
25.4.5.2.4 Condition flags
25.4.5.2.5 Examples
25.4.5.3.1 Syntax
25.4.5.3 ASR, LSL, LSR, and ROR
BICS {Rd,} Rn, Rm
where:
The AND, EOR, and ORR instructions perform bitwise AND, exclusive OR, and inclusive
OR operations on the values in Rn and Rm.
The BIC instruction performs an AND operation on the bits in Rn with the logical negation
of the corresponding bits in the value of Rm.
The condition code flags are updated on the result of the operation, see
Section
In these instructions, Rd, Rn, and Rm must only specify R0-R7.
These instructions:
Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, and Rotate Right.
ASRS {Rd,} Rm, Rs
ASRS {Rd,} Rm, #imm
LSLS {Rd,} Rm, Rs
LSLS {Rd,} Rm, #imm
LSRS {Rd,} Rm, Rs
LSRS {Rd,} Rm, #imm
RORS {Rd,} Rm, Rs
•
•
Rd is the destination register.
Rn is the register holding the first operand and is the same as the destination register.
Rm second register.
update the N and Z flags according to the result
do not affect the C or V flag.
ANDS
25.4.3.6.1.
ORRS
ANDS
EORS
BICS
R2, R2, R1
All information provided in this document is subject to legal disclaimers.
R2, R2, R5
R5, R5, R8
R7, R7, R6
R0, R0, R1
Rev. 1 — 15 February 2011
Chapter 25: LPC122x Appendix ARM Cortex-M0
UM10441
© NXP B.V. 2011. All rights reserved.
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