OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 393

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
Table 369. ADC, ADD, RSB, SBC and SUB operand restrictions
UM10441
User manual
Instruction Rd
ADCS
ADD
ADDS
RSBS
SBCS
SUB
SUBS
25.4.5.1.4 Examples
25.4.5.2.1 Syntax
25.4.5.2 AND, ORR, EOR, and BIC
R0-R7
R0-R15
R0-R7
SP
R0-R7
R0-R7
R0-R7
R0-R7
R0-R7
SP
R0-R7
R0-R7
R0-R7
The following shows two instructions that add a 64-bit integer contained in R0 and R1 to
another 64-bit integer contained in R2 and R3, and place the result in R0 and R1.
64-bit addition:
Multiword values do not have to use consecutive registers. The following shows
instructions that subtract a 96-bit integer contained in R1, R2, and R3 from another
contained in R4, R5, and R6. The example stores the result in R4, R5, and R6.
96-bit subtraction:
The following shows the RSBS instruction used to perform a 1's complement of a single
register.
Logical AND, OR, Exclusive OR, and Bit Clear.
ANDS {Rd,} Rn, Rm
ORRS {Rd,} Rn, Rm
EORS {Rd,} Rn, Rm
Arithmetic negation:
R0-R7
SP
R0-R7
R0-R7
R0-R7
R0-R7
R0-R7
R0-R7
R0-R7
R0-R7
Rn
R0-R15
SP or PC
SP
ADDS
SUBS
ADCS
SBCS
SBCS
R0, R0, R2
R4, R4, R1
Rm
R0-R7
R0-PC
-
-
-
-
R0-R7
-
R0-R7
-
-
-
R0-R7
All information provided in this document is subject to legal disclaimers.
R1, R1, R3
R5, R5, R2
R6, R6, R3
Rev. 1 — 15 February 2011
imm
-
-
0-1020
0-508
0-7
0-255
-
-
-
0-508
0-7
0-255
-
; add the least significant words
; subtract the least significant words
RSBS
; add the most significant words with carry
; subtract the middle words with carry
; subtract the most significant words with carry
R7, R7, #0
Restrictions
Rd and Rn must specify the same register.
Rd and Rn must specify the same register.
Rn and Rm must not both specify PC.
Immediate value must be an integer multiple of four.
Immediate value must be an integer multiple of four.
-
Rd and Rn must specify the same register.
-
-
Rd and Rn must specify the same register.
Immediate value must be an integer multiple of four.
-
Rd and Rn must specify the same register.
-
Chapter 25: LPC122x Appendix ARM Cortex-M0
; subtract R7 from zero
UM10441
© NXP B.V. 2011. All rights reserved.
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