OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 364

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
25.3.2 Memory model
The CMSIS includes address definitions and data structures for the core peripherals in the
Cortex-M0 processor. It also includes optional interfaces for middleware components
comprising a TCP/IP stack and a Flash file system.
The CMSIS simplifies software development by enabling the reuse of template code, and
the combination of CMSIS-compliant software components from various middleware
vendors. Software vendors can expand the CMSIS to include their peripheral definitions
and access functions for those peripherals.
This document includes the register names defined by the CMSIS, and gives short
descriptions of the CMSIS functions that address the processor core and the core
peripherals.
Remark: This document uses the register short names defined by the CMSIS. In a few
cases these differ from the architectural short names that might be used in other
documents.
The following sections give more information about the CMSIS:
This section describes the processor memory map and the behavior of memory accesses.
The processor has a fixed memory map that provides up to 4GB of addressable memory.
The memory map is:
For a Cortex-M0 microcontroller system, CMSIS defines:
•
•
•
•
•
•
•
a common way to:
– access peripheral registers
– define exception vectors
the names of:
– the registers of the core peripherals
– the core exception vectors
a device-independent interface for RTOS kernels.
Section 25.3.5.3 “Power management programming hints”
Section 25.4.2 “Intrinsic functions”
Section 25.5.2.1 “Accessing the Cortex-M0 NVIC registers using CMSIS”
Section 25.5.2.8.1 “NVIC programming
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
Chapter 25: LPC122x Appendix ARM Cortex-M0
hints”.
UM10441
© NXP B.V. 2011. All rights reserved.
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