OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 346

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
Table 345. channel_cfg bit assignments
UM10441
User manual
Bit
20:18
23:21
25:24
Name
src_prot_ctrl3:1 Set the bits to control AHB Lite access protection when the controller reads the source data.
dst_prot_ctrl3:1 Set the bits to control AHBLite access protection when the controller writes the destination data.
src_size
Description
Bit [20] controls the state access as follows:
0 = access is non-cacheable.
1 = access is cacheable.
Bit [19] controls the access as follows:
0 = access is non-bufferable.
1 = access is bufferable.
Bit [18] controls the access as follows:
0 = access is non-privileged.
1 = access is privileged.
For normal operation of the DMA controller, set bits 21 to 23 to zero.
Bit [23]: reserved.
Bit [22] controls the access as follows:
0 = access is non-bufferable.
1 = access is bufferable.
Bit [21] controls the access as follows:
0 = access is non-privileged.
1 = access is privileged.
Set the bits to match the size of the source data:
00 = byte
01 = half-word
10 = word
11 = reserved
All information provided in this document is subject to legal disclaimers.
…continued
Rev. 1 — 15 February 2011
Chapter 21: LPC122x General purpose micro DMA controller
UM10441
© NXP B.V. 2011. All rights reserved.
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