OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 328

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
21.6 Register description
Table 320. Register overview: micro DMA (base address 0x4004 C000)
UM10441
User manual
Name
DMA_STATUS
DMA_CFG
CTRL_BASE_PTR
ATL_CTRL_BASE_PTR
DMA_WAITONREQ_STATUS RO
CHNL_SW_REQUEST
CHNL_USEBURST_SET
CHNL_USEBURST_CLR
CHNL_REQ_MASK_SET
CHNL_REQ_MASK_CLR
CHNL_ENABLE_SET
CHNL_ENABLE_CLR
CHNL_PRI_ALT_SET
CHNL_PRI_ALT_CLR
CHNL_PRIORITY_SET
CHNL_PRIORITY_CLR
-
ERR_CLR
-
CHNL_IRQ_STATUS
IRQ_ERR_ENABLE
CHNL_IRQ_ENABLE
21.6.1 DMA status register
Table 320
This register is a read-only register and returns the status of the micro DMA controller.
This register cannot be read when the micro DMA controller is in the reset state.
Access Address offset Description
RO
R/W
RO
WO
R/W
R/W
WO
R/W
WO
R/W
R/W
WO
-
R/W
-
R/W
R/W
R/W
WO
WO
WO
shows the micro DMA register map.
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x040 - 0x048
0x04C
0x050 - 0x07C
0x080
0x084
0x088
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
Chapter 21: LPC122x General purpose micro DMA controller
DMA status register
DMA configuration register
Channel control base pointer register
Channel alternate control base pointer register
Channel wait on request status register
Channel software request register
Channel useburst set register
Channel useburst clear register
Channel request mask set register
Channel request mask clear register
Channel enable set register
Channel enable clear register
Channel primary-alternate set register
Channel primary-alternate clear register
Channel priority set register
Channel priority clear register
Reserved
Bus error clear register
Reserved
Channel DMA interrupt status register
DMA error interrupt enable register
Channel DMA interrupt enable register
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
-
-
0x0000 0000
<tbd>
-
0x0000 0000
-
0x0000 0000
-
0x0000 0000
-
0x0000 0000
-
0x0000 0000
-
-
0x0000 0000
-
0x0000 0000
0x0000 0000
0x0000 0000
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