OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 175

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
10.5.12.1 Baudrate calculation
Table 176. UART Fractional Divider Register (FDR - address 0x4000 C028) bit description
This register controls the clock pre-scaler for the baud rate generation. The reset value of
the register keeps the fractional capabilities of UART disabled making sure that UART is
fully software and hardware compatible with UARTs not equipped with this feature.
The UART baudrate can be calculated as (n = 1):
Where UART_PCLK is the peripheral clock, DLM and DLL are the standard UART baud
rate divider registers, and DIVADDVAL and MULVAL are UART fractional baudrate
generator specific parameters.
The value of MULVAL and DIVADDVAL should comply to the following conditions:
The value of the FDR should not be modified while transmitting/receiving data or data may
be lost or corrupted.
If the FDR register value does not comply to these two requests, then the fractional divider
output is undefined. If DIVADDVAL is zero then the fractional divider is disabled, and the
clock will not be divided.
UART can operate with or without using the Fractional Divider. In real-life applications it is
likely that the desired baudrate can be achieved using several different Fractional Divider
settings. The following algorithm illustrates one way of finding a set of DLM, DLL,
MULVAL, and DIVADDVAL values. Such set of parameters yields a baudrate with a
relative error of less than 1.1% from the desired one.
Bit
3:0
7:4
31:8
1. 1 ≤ MULVAL ≤ 15
2. 0 ≤ DIVADDVAL < 15
3. DIVADDVAL<MULVAL
Symbol
DIVADDVAL
MULVAL
-
UART
All information provided in this document is subject to legal disclaimers.
baudrate
Description
Baud-rate generation pre-scaler divisor value. If this field is 0,
fractional baud-rate generator will not impact the UARTn
baudrate.
Baud-rate pre-scaler multiplier value. This field must be greater
or equal 1 for UARTn to operate properly, regardless of whether
the fractional baud-rate generator is used or not.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Rev. 1 — 15 February 2011
=
----------------------------------------------------------------------------------------------------------------------------------
16
×
(
256
×
U1DLM
+
PCLK
U1DLL
)
Chapter 10: LPC122x UART1
×
⎛
⎝
1
+
DivAddVal
---------------------------- -
MulVal
UM10441
© NXP B.V. 2011. All rights reserved.
⎞
⎠
Reset
value
0
1
0
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