OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 147

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
9.5.10 UART Modem Status Register
Table 149. UART Line Status Register (LSR - address 0x4000 8014, Read Only) bit
The MSR is a read-only register that provides status information on the modem input
signals. MSR[3:0] is cleared on MSR read. Note that modem signals have no direct effect
on the UART operation. They facilitate the software implementation of modem signal
operations.
Bit
3
4
5
6
7
31:8 -
Symbol
FE
BI
THRE
TEMT
RXFE
description
All information provided in this document is subject to legal disclaimers.
Value Description
-
0
1
0
1
0
1
0
1
0
1
Rev. 1 — 15 February 2011
…continued
Framing Error. When the stop bit of a received character is a
logic 0, a framing error occurs. A LSR read clears LSR[3]. The
time of the framing error detection is dependent on FCR0.
Upon detection of a framing error, the RX will attempt to
re-synchronize to the data and assume that the bad stop bit is
actually an early start bit. However, it cannot be assumed that
the next received byte will be correct even if there is no
Framing Error.
Note: A framing error is associated with the character at the
top of the UART RBR FIFO.
Framing error status is inactive.
Framing error status is active.
Break Interrupt. When RXD1 is held in the spacing state (all
zeros) for one full character transmission (start, data, parity,
stop), a break interrupt occurs. Once the break condition has
been detected, the receiver goes idle until RXD1 goes to
marking state (all ones). A LSR read clears this status bit. The
time of break detection is dependent on FCR[0].
Note: The break interrupt is associated with the character at
the top of the UART RBR FIFO.
Break interrupt status is inactive.
Break interrupt status is active.
Transmitter Holding Register Empty. THRE is set immediately
upon detection of an empty UART THR and is cleared on a
THR write.
THR contains valid data.
THR is empty.
Transmitter Empty. TEMT is set when both THR and TSR are
empty; TEMT is cleared when either the TSR or the THR
contain valid data.
THR and/or the TSR contains valid data.
THR and the TSR are empty.
Error in RX FIFO. LSR[7] is set when a character with a RX
error such as framing error, parity error or break interrupt, is
loaded into the RBR. This bit is cleared when the LSR register
is read and there are no subsequent errors in the UART FIFO.
RBR contains no UART RX errors or FCR[0]=0.
UART RBR contains at least one UART RX error.
Reserved
Chapter 9: LPC122x UART0 with modem control
UM10441
© NXP B.V. 2011. All rights reserved.
147 of 442
Reset
Value
0
0
1
1
0
-