OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 365
OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
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UM10441
User manual
25.3.2.1 Memory regions, types and attributes
The processor reserves regions of the Private peripheral bus (PPB) address range for
core peripheral registers, see
The memory map is split into regions. Each region has a defined memory type, and some
regions have additional memory attributes. The memory type and attributes determine the
behavior of accesses to the region.
The memory types are:
Normal — The processor can re-order transactions for efficiency, or perform speculative
reads.
Device — The processor preserves transaction order relative to other transactions to
Device or Strongly-ordered memory.
Fig 63. Cortex-M0 memory map
For the LPC122x specific implementation of the memory map, see
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
Private peripheral bus
Section
External device
External RAM
Peripheral
Device
SRAM
Code
25–25.2.
Chapter 25: LPC122x Appendix ARM Cortex-M0
511MB
1.0GB
1.0GB
0.5GB
0.5GB
0.5GB
1MB
0xFFFFFFFF
0xE0100000
0xE00FFFFF
0xE0000000
0xDFFFFFFF
0xA0000000
0x9FFFFFFF
0x60000000
0x5FFFFFFF
0x40000000
0x3FFFFFFF
0x20000000
0x1FFFFFFF
0x00000000
Figure
2.
UM10441
© NXP B.V. 2011. All rights reserved.
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