OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 188

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
11.7.7.1 Interrupt in Monitor mode
Table 190. I
Remark: The ENA_SCL and MATCH_ALL bits have no effect if the MM_ENA is ‘0’ (i.e. if
the module is NOT in monitor mode).
All interrupts will occur as normal when the module is in monitor mode. This means that
the first interrupt will occur when an address-match is detected (any address received if
the MATCH_ALL bit is set, otherwise an address matching one of the four address
registers).
Subsequent to an address-match detection, interrupts will be generated after each data
byte is received for a slave-write transfer, or after each byte that the module “thinks” it has
transmitted for a slave-read transfer. In this second case, the data register will actually
contain data transmitted by some other slave on the bus which was actually addressed by
the master.
Bit Symbol
0
1
2
31
:3
MM_ENA
ENA_SCL
MATCH_ALL
-
2
C Monitor mode control register (MMCTRL - 0x4000 001C) bit description
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
0
1
-
Rev. 1 — 15 February 2011
Monitor mode enable.
Monitor mode disabled.
The I
output will be forced high. This will prevent the I
from outputting data of any kind (including ACK) onto the I
data bus.
Depending on the state of the ENA_SCL bit, the output may
be also forced high, preventing the module from having control
over the I
SCL output enable.
When this bit is cleared to 0, the SCL output will be forced high
when the module is in monitor mode. As described above, this
will prevent the module from having any control over the I
clock line.
When this bit is set, the I
control over the clock line that it would in normal operation.
This means that, acting as a slave peripheral, the I
can stretch the clock line (hold it low) until it has had time to
respond to an I
Remark:
has the ability to stall the bus, interrupt response time becomes
important. To give the part more time to respond to an I
under these conditions, a DATA _BUFFER register is used to hold
received data for a full 9-bit word transmission time.
Select interrupt register match.
When this bit is cleared, an interrupt will only be generated
when a match occurs to one of the (up-to) four address
registers described above. That is, the module will respond
as a normal slave as far as address-recognition is concerned.
When this bit is set to 1 and the I
interrupt will be generated on ANY address received. This will
enable the part to monitor all traffic on the bus.
Reserved.
2
C module will enter monitor mode. In this mode the SDA
2
When the ENA_SCL bit is cleared and the I
C clock line.
2
C interrupt.
Chapter 11: LPC122x I2C-bus controller
2
C module may exercise the same
2
C is in monitor mode, an
2
2
C module
2
C no longer
C interrupt
UM10441
2
© NXP B.V. 2011. All rights reserved.
C module
2
2
C
C
188 of 442
Reset
value
0
0
0
-