OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 385
OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
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UM10441
User manual
25.4.4.1.1 Syntax
25.4.4.1.2 Operation
25.4.4.1 ADR
25.4.4 Memory access instructions
Table 366. Condition code suffixes
Table 367
Table 367. Access instructions
Generates a PC-relative address.
ADR Rd, label
where:
ADR generates an address by adding an immediate value to the PC, and writes the result
to the destination register.
Suffix
PL
VS
VC
HI
LS
GE
LT
GT
LE
AL
Mnemonic
LDR{type}
LDR
POP
PUSH
STM
STR{type}
STR{type}
Rd is the destination register.
label is a PC-relative expression. See
shows the memory access instructions:
Flags
N = 0
V = 1
V = 0
C = 1 and Z = 0
C = 0 or Z = 1
N = V
N != V
Z = 0 and N = V
Z = 1 and N != V
Can have any value
All information provided in this document is subject to legal disclaimers.
Brief description
Load Register using register offset
Load Register from PC-relative address
Pop registers from stack
Push registers onto stack
Store Multiple registers
Store Register using immediate offset
Store Register using register offset
Rev. 1 — 15 February 2011
Meaning
Positive or zero
Overflow
No overflow
Lower or same, unsigned
Greater than or equal, signed
Less than, signed
Less than or equal, signed
Always. This is the default when no suffix is specified.
Higher, unsigned
Greater than, signed
Chapter 25: LPC122x Appendix ARM Cortex-M0
Section
25–25.4.3.5.
UM10441
See
Section 25–25.4.4.
3
Section 25–25.4.4.
4
Section 25–25.4.4.
6
Section 25–25.4.4.
6
Section 25–25.4.4.
5
Section 25–25.4.4.
2
Section 25–25.4.4.
3
© NXP B.V. 2011. All rights reserved.
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