OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 206

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
Fig 25. Format and states in the Slave Transmitter mode
11.10.4 Slave Transmitter mode
reception of the own
Slave address and
one or more Data
bytes all are
acknowledged
last data byte
transmitted. Switched
to Not Addressed
Slave (AA bit in
I2CON = “0”)
arbitration lost as
Master and
addressed as Slave
DATA
n
In the slave transmitter mode, a number of data bytes are transmitted to a master receiver
(see
CON have been initialized, the I
address followed by the data direction bit which must be “1” (R) for the I
operate in the slave transmitter mode. After its own slave address and the R bit have been
received, the serial interrupt flag (SI) is set and a valid status code can be read from STAT.
This status code is used to vector to a state service routine, and the appropriate action to
be taken for each of these status codes is detailed in
mode may also be entered if arbitration is lost while the I
(see state 0xB0).
If the AA bit is reset during a transfer, the I
and enter state 0xC0 or 0xC8. The I
and will ignore the master receiver if it continues the transfer. Thus the master receiver
receives all 1s as serial data. While AA is reset, the I
slave address or a General Call address. However, the I
address recognition may be resumed at any time by setting AA. This means that the AA
bit may be used to temporarily isolate the I
A
Figure
S
from Master to Slave
from Slave to Master
any number of data bytes and their associated
Acknowledge bits
this number (contained in I2STA) corresponds to a defined state of
the I
25). Data transfer is initialized as in the slave receiver mode. When ADR and
2
C bus
SLA
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
R
A8H
B0H
A
A
2
C block waits until it is addressed by its own slave
DATA
2
C block is switched to the not addressed slave mode
B8H
2
A
C block will transmit the last byte of the transfer
2
C block from the I
Chapter 11: LPC122x I2C-bus controller
DATA
2
C block does not respond to its own
Table
C8H
C0H
2
A
A
2
C-bus is still monitored, and
C block is in the master mode
202. The slave transmitter
P OR S
ALL ONES
2
C-bus.
UM10441
P OR S
© NXP B.V. 2011. All rights reserved.
2
C block to
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