OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 326

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
21.4.1 Memory regions accessible by the micro DMA controller
The DMA controller supports data transfer sizes of 8, 16, or 32 bit (byte, half-word, or
word), configured through the channel control data structure (see
data transfer size and the destination data transfer size must be the same.
The controller always uses 32-bit data transfers when it accesses a channel control data
structure.
The DMA control block contains the control logic that performs the following tasks:
Remark: Peripheral-to-peripheral transactions are not supported because each channel
only provides a single DMA request interface.
The DMA channel control data structure is written to and updated in SRAM.
Memory-to-memory DMA transfers are supported as software-controlled transfers.
configuration
Fig 55. Micro DMA controller block diagram
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Arbitrates the incoming requests.
Indicates which channel is active.
Indicates when a channel is complete.
Indicates when an error has occurred on the AHB-Lite interface.
Enables slow peripherals to stall the completion of a DMA cycle.
Waits for a request to clear before completing a DMA cycle.
Performs multiple or single DMA transfers for each request.
Performs the following types of DMA transfers:
– memory-to-memory
– memory-to-peripheral
– peripheral-to-memory
control
active channel
channel done
DMA stall
requests
mode
APB BUS
error
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
INTERFACE
REGISTER
Chapter 21: LPC122x General purpose micro DMA controller
APB
Micro DMA
CONTROL
DMA
INTERFACE
MASTER
AHB-Lite
Table
AHB BUS
UM10441
© NXP B.V. 2011. All rights reserved.
345). The source
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DMA data
transfer