OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 145

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
Fig 5.
UART Rx
UART Rx
UART Rx
FIFO read
FIFO level
RTS pin
Auto-RTS Functional Timing
9.5.8.1.2 Auto-CTS
start
N-1
byte N
If Auto-RTS mode is disabled, the RTSen bit controls the RTS output of the UART. If
Auto-RTS mode is enabled, hardware controls the RTS output, and the actual value of
RTS will be copied in the RTS Control bit of the UART. As long as Auto-RTS is enabled,
the value of the RTS Control bit is read-only for software.
Example: Suppose the UART operating in type ‘550 mode has the trigger level in FCR set
to 0x2, then, if Auto-RTS is enabled, the UART will deassert the RTS output as soon as
the receive FIFO contains 8 bytes
reasserted as soon as the receive FIFO hits the previous trigger level: 4 bytes.
The Auto-CTS function is enabled by setting the CTSen bit. If Auto-CTS is enabled the
transmitter circuitry in the TSR module checks CTS input before sending the next data
byte. When CTS is active (low), the transmitter sends the next byte. To stop the
transmitter from sending the following byte, CTS must be released before the middle of
the last stop bit that is currently being sent. In Auto-CTS mode a change of the CTS signal
does not trigger a modem status interrupt unless the CTS Interrupt Enable bit is set, Delta
CTS bit in the MSR will be set though.
Modem Status interrupt.
Table 148. Modem status interrupt generation
Enable
modem
status
interrupt
(ER[3])
0
1
1
1
1
1
1
1
1
stop
start
N
CTSen
(MCR[7])
x
0
0
0
1
1
1
1
1
All information provided in this document is subject to legal disclaimers.
bits0..7
N-1
Rev. 1 — 15 February 2011
CTS
interrupt
enable
(IER[7])
x
x
x
x
0
0
1
1
1
stop
N-2
N-1
(Table 145 on page
Chapter 9: LPC122x UART0 with modem control
Delta CTS
(MSR[0])
x
0
1
x
x
x
0
1
x
Table 148
N-2
lists the conditions for generating a
Delta DCD or trailing edge
RI or
Delta DSR (MSR[3] or
MSR[2] or MSR[1])
x
0
x
1
0
1
0
x
1
M+2
142). The RTS output will be
M+1
M
start
UM10441
© NXP B.V. 2011. All rights reserved.
bits0..7
M-1
Modem
status
interrupt
No
No
Yes
Yes
No
Yes
No
Yes
Yes
145 of 442
stop