OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 342

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
21.7.5 DMA control
The controller uses the SRAM to enable it to access two pointers and the control
information that it requires for each channel.The channel control information is contained
in the channel control data structure, and the source and destination addresses for the
DMA transfer are defined by the source end and destination end pointers.
Fig 56. DMA ping-pong cycle
request/arbitrate
request/arbitrate
request/arbitrate
request/arbitrate
request/arbitrate
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
Chapter 21: LPC122x General purpose micro DMA controller
channel c, cycle 5
channel c, cycle 1
channel c, cycle 3
primary channel
data structure
control
request/arbitrate
request/arbitrate
request/arbitrate
request/arbitrate
request/arbitrate
cycle_ctrl = 011; 2
cycle_ctrl = 011; 2
cycle_ctrl = 011; 2
N = 2
N = 3
alternate channel
R
channel c, cycle 4
channel c, cycle 2
R
data structure
R
= 4, N = 6
= 2, N = 2
invalid cycle
= 4, N = 7
channel c,
control
cycle_ctrl = 011; 2
cycle_ctrl = 000
cycle_ctrl = 011; 2
N = 8
N = 4
N = 1
UM10441
dma_done[c]
dma_done[c]
dma_done[c]
dma_done[c]
dma_done[c]
© NXP B.V. 2011. All rights reserved.
R
R
= 4, N = 5
= 4, N = 12
342 of 442