OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 65
OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
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NXP Semiconductors
UM10441
User manual
6.4.3 PIO0_20 register
Table 63.
Table 64.
Bit
12:11
15:13
31:16
Bit
2:0
3
4
5
6
7
8
9
Symbol
S_MODE
CLK_DIV
-
Symbol
FUNC
-
MODE
-
INV
ADMODE
-
DRV
PIO0_19 register (PIO0_19, address 0x4004 4008) bit description
PIO0_20 register (PIO0_20, address 0x4004 400C) bit description
All information provided in this document is subject to legal disclaimers.
Value
0x0
0x1
0x2
0x3
Value
0x0
0x1
0x2
0x3
0x4
0
1
0
1
0
1
0
1
0x0
0x1
0x2
0x3
0x4
0x5
0x6
-
Rev. 1 — 15 February 2011
Description
Sample mode
Bypass input filter.
Input pulses shorter than one filter clock are rejected.
Select peripheral clock divider for input filter sampling clock.
IOCONFIGCLKDIV0.
IOCONFIGCLKDIV1.
IOCONFIGCLKDIV2.
IOCONFIGCLKDIV3.
IOCONFIGCLKDIV4.
IOCONFIGCLKDIV5.
IOCONFIGCLKDIV6.
Reserved.
Description
Selects pin function.
Selects function PIO0_20.
Reserved. Do not use.
Select function ACMP0_I1.
Select function CT32B0_CAP2.
Select function CT32B0_MAT2.
Reserved
Selects function mode (on-chip pull-up resistor control).
Inactive (pull-up resistor not enabled).
Pull-up resistor enabled.
Reserved.
Invert input
Input not inverted.
Input inverted.
Analog/Digital mode
Analog mode enabled.
Digital mode enabled.
Reserved.
Drive current mode (Normal-drive pin).
Low mode current selected.
High mode current selected.
Input pulses shorter than two filter clocks are rejected.
Input pulses shorter than three filter clocks are rejected.
Chapter 6: LPC122x I/O configuration (IOCONFIG)
UM10441
© NXP B.V. 2011. All rights reserved.
65 of 442
Reset
value
00
000
0
Reset
value
000
0
1
0
0
1
0
0
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