OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 232
OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
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UM10441
User manual
Fig 30. SPI frame format with CPOL=0 and CPHA=0 (a) Single and b) Continuous Transfer)
a. Single transfer with CPOL=0 and CPHA=0
b. Continuous transfer with CPOL=0 and CPHA=0
SSEL
MOSI
MISO
SCK
12.7.2.2 SPI format with CPOL=0,CPHA=0
MSB
MSB
The CPHA control bit selects the clock edge that captures data and allows it to change
state. It has the most impact on the first bit transmitted by either allowing or not allowing a
clock transition before the first data capture edge. When the CPHA phase control bit is
LOW, data is captured on the first clock edge transition. If the CPHA clock phase control
bit is HIGH, data is captured on the second clock edge transition.
Single and continuous transmission signal sequences for SPI format with CPOL = 0,
CPHA = 0 are shown in
In this configuration, during idle periods:
If the SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SSEL master signal being driven LOW. This causes slave
data to be enabled onto the MISO input line of the master. Master’s MOSI is enabled.
One half SCK period later, valid master data is transferred to the MOSI pin. Now that both
the master and slave data have been set, the SCK master clock pin goes HIGH after one
further half SCK period.
The data is now captured on the rising and propagated on the falling edges of the SCK
signal.
•
•
•
The CLK signal is forced LOW.
SSEL is forced HIGH.
The transmit MOSI/MISO pad is in high impedance.
SSEL
MOSI
MISO
SCK
4 to 16 bit
All information provided in this document is subject to legal disclaimers.
MSB
Rev. 1 — 15 February 2011
LSB
LSB
MSB
Figure
Q
30.
4 to 16 bit
MSB
MSB
LSB
LSB
Chapter 12: LPC122x SSP controller
Q
4 to 16 bit
UM10441
© NXP B.V. 2011. All rights reserved.
LSB
LSB
Q
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