OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 229
OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
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UM10441
User manual
12.6.8 SSP Masked Interrupt Status Register
12.6.9 SSP Interrupt Clear Register
Table 212. SSP Raw Interrupt Status register (RIS - address 0x4004 0018) bit description
This read-only register contains a 1 for each interrupt condition that is asserted and
enabled in the IMSC. When an SSP interrupt occurs, the interrupt service routine should
read this register to determine the cause(s) of the interrupt.
Table 213. SSP Masked Interrupt Status register (MIS -address 0x4004 001C) bit description
Software can write one or more one(s) to this write-only register, to clear the
corresponding interrupt condition(s) in the SSP controller. Note that the other two interrupt
conditions can be cleared by writing or reading the appropriate FIFO, or disabled by
clearing the corresponding bit in IMSC.
Bit
0
1
2
3
31:4
Bit
0
1
2
3
31:4
Symbol
RORRIS
RTRIS
RXRIS
TXRIS
-
Symbol
RORMIS
RTMIS
RXMIS
TXMIS
-
All information provided in this document is subject to legal disclaimers.
Description
This bit is 1 if another frame was completely received while the
RxFIFO was full. The ARM spec implies that the preceding
frame data is overwritten by the new frame data when this
occurs.
This bit is 1 if the Rx FIFO is not empty, and has not been read
for a “time-out period”. The time-out period is the same for
master and slave modes and is determined by the SSP bit
rate: 32 bits at PCLK / (CPSDVSR × [SCR+1]).
This bit is 1 if the Rx FIFO is at least half full.
This bit is 1 if the Tx FIFO is at least half empty.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Description
This bit is 1 if another frame was completely received while the
RxFIFO was full, and this interrupt is enabled.
This bit is 1 if the Rx FIFO is not empty, has not been read for
a “time-out period”, and this interrupt is enabled. The time-out
period is the same for master and slave modes and is
determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR
× [SCR+1]).
This bit is 1 if the Rx FIFO is at least half full, and this interrupt
is enabled.
This bit is 1 if the Tx FIFO is at least half empty, and this
interrupt is enabled.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Rev. 1 — 15 February 2011
Chapter 12: LPC122x SSP controller
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
0
0
0
1
NA
Reset value
0
0
0
0
NA
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