OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 41

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
4.5.38 Deep-sleep mode configuration register
Table 45.
This register controls the behavior of the WatchDog (WD) oscillator and the BOD circuit
when the device enters Deep-sleep mode. In addition, the WD oscillator behavior is
influenced by the WDLOCKCLK bit in the WDMODE register
blocks are shut down in Deep-sleep mode.
This register must be written before entering Deep-sleep mode and before setting the
WDT lock bit WDLOCKCLK with one of the four values shown in
Table 46.
Table 47.
Remark: Failure to initialize and program this register correctly may result in undefined
behavior of the microcontroller. The values listed in
values allowed for PDSLEEPCFG register.
To select the appropriate power configuration for Deep-sleep mode, consider the
following:
Bit
15
16
17
18
31:19 -
Configuration
BOD on
BOD off
Configuration
BOD on
BOD off
•
•
BOD: Leaving the BOD circuit enabled will protect the part from a low voltage event
occurring while the part is in Deep-sleep mode. However, the BOD circuit causes an
WD oscillator: The watchdog oscillator can be left running in Deep-sleep mode to
provide a clock for the watchdog timer if needed for timing a wake-up event (see
Section 4.8.3
additional current drain in Deep-sleep mode.
Symbol
SRGPIO2
-
SRDMA
SRRTC
Start logic signal status register 1 (STARTSRP1, address 0x4004 821C) bit
description
Allowed values for PDSLEEPCFG register if WDLOCKCLK = 0 (WD oscillator not
locked)
Allowed values for PDSLEEPCFG register if WDLOCKCLK = 1 (WD oscillator
locked)
All information provided in this document is subject to legal disclaimers.
for details). In this case, the watchdog oscillator analog output
Description
Start signal status for start logic interrupt GPIO2.
0 = No start signal received.
1 = Start signal pending.
Reserved
Start signal status for start logic interrupt DMA.
0 = No start signal received.
1 = Start signal pending.
Start signal status for start logic interrupt RTC.
0 = No start signal received.
1 = Start signal pending.
Reserved
Rev. 1 — 15 February 2011
…continued
WD oscillator on
PDSLEEPCFG = 0x0000 FFB7
PDSLEEPCFG = 0x0000 FFBF
WD oscillator on
PDSLEEPCFG = 0x0000 FFB7
PDSLEEPCFG = 0x0000 FFBF
Chapter 4: LPC122x System control (SYSCON)
Table 46
WD oscillator off
not allowed
not allowed
WD oscillator off
PDSLEEPCFG = 0x0000 FFF7
PDSLEEPCFG = 0x0000 FFFF
(Table
and
Table
Table 47
264). All other analog
UM10441
© NXP B.V. 2011. All rights reserved.
46:
are the only
Reset
value
0
0
0
0
-
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