OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 24

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
4.5.15 SSP clock divider register
4.5.16 UART0 clock divider register
Table 21.
This register configures the SSP peripheral clock SSP_PCLK. The SSP_PCLK can be
shut down by setting the DIV bits to 0x0.
Table 22.
This register configures the UART0 peripheral clock UART0_PCLK. The UART0_PCLK
can be shut down by setting the DIV bits to 0x0.
Remark: Note that the UART0 pins must be configured in the IOCON block before the
UART0 clock can be enabled.
Bit
19
20
27:21
28
29
30
31
Bit
7:0
31:8
Symbol
RTC
CMP
-
-
GPIO2
GPIO1
GPIO0
Symbol
DIV
-
System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit
description
SSP clock divider register (SSPCLKDIV, address 0x4004 8094) bit description
All information provided in this document is subject to legal disclaimers.
Description
SSP0_PCLK clock divider values
0: Disable SSP0_PCLK.
1: Divide by 1.
to
255: Divide by 255.
Reserved
Rev. 1 — 15 February 2011
…continued
Value
0
1
0
1
0
1
0
1
0
1
-
-
Description
Enables clock for RTC.
Remark: The RTC clock source must be selected
before the RTC is enabled through this bit (see
Table
Disable
Enable
Enables clock for comparator.
Disable
Enable
Reserved
Reserved. Write as zero.
Enables clock for GPIO port 2.
Disable
Enable
Enables clock for GPIO port 1.
Disable
Enable
Enables clock for GPIO port 0.
Disable
Enable
58).
Chapter 4: LPC122x System control (SYSCON)
UM10441
© NXP B.V. 2011. All rights reserved.
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Reset
value
1
1
0
1
1
1
1
Reset
value
0
0x00