OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 308

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
Table 286. Code Read Protection options
Table 287. Code Read Protection hardware/software interaction
Name
NO_ISP
CRP1
CRP2
CRP3
CRP option
No
No
No
CRP1
CRP1
0x4E69 7370
Pattern
programmed in
0x0000 02FC
0x12345678
0x87654321
0x43218765
User Code
Valid
No
Yes
Yes
Yes
Yes
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
Description
Prevents sampling of pin PIO0_12 for entering ISP mode. PIO0_12
is available for other uses. Flash contents are not protected, and the
flash can be reprogrammed through the SWD interface.
Access to chip via the JTAG pins is disabled. This mode allows
partial flash update using the following ISP commands and
restrictions:
This mode is useful when CRP is required and flash field updates are
needed but all sectors can not be erased. Since compare command
is disabled in case of partial updates the secondary loader should
implement checksum mechanism to verify the integrity of the flash.
Access to chip via the JTAG pins is disabled. The following ISP
commands are disabled:
When CRP2 is enabled the ISP erase command only allows erasure
of all user sectors.
Access to chip via the JTAG pins is disabled. ISP entry by pulling
PIO0_12 LOW is disabled if a valid user code is present in flash
sector 0.
This mode effectively disables ISP override using PIO0_12 pin. It is
up to the user’s application to provide a flash update mechanism
using IAP calls or call reinvoke ISP command to enable flash update
via UART.
Caution: If CRP3 is selected, no future factory testing can be
performed on the device.
•
•
•
•
•
•
•
•
•
•
PIO0_12 pin
at reset
x
High
Low
High
Low
Write to RAM command cannot access RAM below 0x1000
0300.
Copy RAM to flash command can not write to Sector 0.
Erase command can erase Sector 0 only when all sectors are
selected for erase.
Compare command is disabled.
Read Memory command is disabled.
Read Memory
Write to RAM
Go
Copy RAM to flash
Compare
JTAG enabled LPC122x
Yes
Yes
Yes
No
No
Chapter 20: LPC122x Flash ISP/IAP
enters ISP
mode
Yes
No
Yes
No
Yes
UM10441
© NXP B.V. 2011. All rights reserved.
partial flash
update in ISP
mode
Yes
NA
Yes
NA
Yes
308 of 442