OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 368
OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
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UM10441
User manual
25.3.2.5.1 Little-endian format
25.3.2.5 Memory endianness
25.3.3.1 Exception states
25.3.3 Exception model
Vector table — If the program changes an entry in the vector table, and then enables the
corresponding exception, use a DMB instruction between the operations. This ensures that
if the exception is taken immediately after being enabled the processor uses the new
exception vector.
Self-modifying code — If a program contains self-modifying code, use an ISB instruction
immediately after the code modification in the program. This ensures subsequent
instruction execution uses the updated program.
Memory map switching — If the system contains a memory map switching mechanism,
use a DSB instruction after switching the memory map. This ensures subsequent
instruction execution uses the updated memory map.
Memory accesses to Strongly-ordered memory, such as the System Control Block, do not
require the use of DMB instructions.
The processor preserves transaction order relative to all other transactions.
The processor views memory as a linear collection of bytes numbered in ascending order
from zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the
second stored word.
memory.
In little-endian format, the processor stores the least significant byte (lsbyte) of a word at
the lowest-numbered byte, and the most significant byte (msbyte) at the
highest-numbered byte. For example:
This section describes the exception model.
Each exception is in one of the following states:
Inactive — The exception is not active and not pending.
Pending — The exception is waiting to be serviced by the processor.
Fig 65. Little-endian format
Address
All information provided in this document is subject to legal disclaimers.
Section 25–25.3.2.5.1
Rev. 1 — 15 February 2011
A+1
A+2
A+3
A
7
Memory
B0
B1
B2
B3
0
lsbyte
msbyte
Chapter 25: LPC122x Appendix ARM Cortex-M0
describes how words of data are stored in
31
B3
24 23
B2
Register
16 15
B1
8 7
UM10441
B0
© NXP B.V. 2011. All rights reserved.
0
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