OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 299

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
19.6.5 A/D Status Register
19.6.6 A/D Trim register
Table 281. A/D Data Registers (DR0 to DR7 - addresses 0x4002 0010 to 0x4002 002C) bit
The A/D Status register allows checking the status of all A/D channels simultaneously.
The DONE and OVERRUN flags appearing in the ADDRn register for each A/D channel
are mirrored in ADSTAT. The interrupt flag (the logical OR of all DONE flags) is also found
in ADSTAT.
Table 282. A/D Status Register (STAT - address 0x4002 0030) bit description
This register will be set by the bootcode on start-up. It contains the trim values for the
ADC. The offset trim values for the ADC can be overwritten by the user.
Table 283. A/D Trim register (TRM - address 0x4002 4034) bit description
Bit
5:0
15:6
29:16 -
30
31
Bit
7:0
15:8
16
31:17 -
Bit
3:0
7:4
31:8
Symbol
DONE
OVERRUN These bits mirror the OVERRRUN status flags that appear in the
ADINT
Symbol
-
RESULT
OVERRUN This bit is 1 in burst mode if the results of one or more conversions
DONE
Symbol
-
ADCOFFS
-
description
All information provided in this document is subject to legal disclaimers.
These bits mirror the DONE status flags that appear in the result
Description
Reserved. These bits always read as zeros.
When DONE is 1, this field contains a binary fraction representing the
voltage on the ADn pin selected by the SEL field, divided by the
voltage on the V
voltage on the ADn pin was less than, equal to, or close to that on
V
equal to, or greater than that on V
Reserved. These bits always read as zeros.
was (were) lost and overwritten before the conversion that produced
the result in the RESULT bits.This bit is cleared by reading this
register.
This bit is set to 1 when an A/D conversion completes. It is cleared
when this register is read.
Description
register for each A/D channel.
result register for each A/D channel. Reading ADSTAT allows
checking the status of all A/D channels simultaneously.
This bit is the A/D interrupt flag. It is one when any of the individual
A/D channel Done flags is asserted and enabled to contribute to the
A/D interrupt via the ADINTEN register.
Reserved. These bits always read as zeros.
Description
Reserved. These bits always read as zeros.
Offset trim bits for ADC operation. Initialized by the boot code. Can
be overwritten by the user.
Reserved. These bits always read as zeros.
SSA
Rev. 1 — 15 February 2011
, while 0x3FF indicates that the voltage on ADn was close to,
DD(3V3)
pin: V/V
REF
REF
. Zero in the field indicates that the
.
Chapter 19: LPC122x ADC
UM10441
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
0
Reset
value
0
X
0
0
0
Reset
value
0
0
0
0