mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 122

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Clock, Reset and Power Management (S12CPMU_UHV)
4.1.2.4
For S12CPMU_UHV Freeze Mode is the same as Run Mode except for RTI and COP which can be
stopped in Active BDM Mode with the RSBCK bit in the CPMUCOP register. Additionally the COP can
be forced to the maximum time-out period in Active BDM Mode. For details please see also the RSBCK
and CR[2:0] bit description field of
Register (CPMUCOP)
122
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Pseudo Stop Mode (PSTP = 1 and OSCE=1)
External oscillator (XOSCLCP) continues to run.
— If COPOSCSEL1=0:
— If COPOSCSEL1=1:
Mode. For this COP configuration (ACLK clock source, CSAD set) a latency time occurs when
entering or exiting (Full, Pseudo) Stop Mode. When bit CSAD is clear the ACLK clock source
is on for the COP during Full Stop Mode and COP is operating.
During Full Stop Mode the RTI counter halts.
After wake-up from Full Stop Mode the Core Clock and Bus Clock are running on PLLCLK
(PLLSEL=1). The COP runs on ACLK and RTI is running on IRCCLK (COPOSCSEL0=0,
RTIOSCSEL=0).
If the respective enable bits are set (PCE=1 and PRE=1) the COP and RTI will continue to run
with a clock derived from the oscillator clock.
The clock configuration bits PLLSEL, COPOSCSEL0, RTIOSCSEL are unchanged.
If the respective enable bit for the RTI is set (PRE=1) the RTI will continue to run with a clock
derived from the oscillator clock.
The clock for the COP is derived from ACLK (trimmable internal RC-Oscillator clock). During
Pseudo Stop Mode the ACLK for the COP can be stopped (COP static) or running (COP active)
depending on the setting of bit CSAD. When bit CSAD is set the ACLK for the COP is stopped
during Pseudo Stop Mode and COP continues to operate after exit from Pseudo Stop Mode.
For this COP configuration (ACLK clock source, CSAD set) a latency time occurs when
entering or exiting (Pseudo, Full) Stop Mode. When bit CSAD is clear the ACLK clock source
is on for the COP during Pseudo Stop Mode and COP is operating.
The clock configuration bits PLLSEL, COPOSCSEL0, RTIOSCSEL are unchanged.
Freeze Mode (BDM active)
When starting up the external oscillator (either by programming OSCE bit
to 1 or on exit from Full Stop Mode with OSCE bit already 1) the software
must wait for a minimum time equivalent to the startup-time of the external
oscillator t
UPOSC
MC9S12VR Family Reference Manual,
before entering Pseudo Stop Mode.
Preliminary - Subject to Change Without Notice
Table 4-12
in
NOTE
Section 4.3.2.9, “S12CPMU_UHV COP Control
Rev. 2.2
Freescale Semiconductor