mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 244

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Interrupt Module (S12SINTV1)
7.1.3
7.1.4
Figure 7-1
1. The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used
244
as upper byte) and 0x00 (used as lower byte).
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2–58 I bit maskable interrupt vector requests (at addresses vector base + 0x0082–0x00F2).
I bit maskable interrupts can be nested.
One X bit maskable interrupt vector request (at address vector base + 0x00F4).
One non-maskable software interrupt request (SWI) or background debug mode vector request (at
address vector base + 0x00F6).
One non-maskable unimplemented op-code trap (TRAP) vector (at address vector base + 0x00F8).
Three system reset vectors (at addresses 0xFFFA–0xFFFE).
Determines the highest priority interrupt vector requests, drives the vector to the bus on CPU
request
Wakes up the system from stop or wait mode when an appropriate interrupt request occurs.
Run mode
This is the basic mode of operation.
Wait mode
In wait mode, the clock to the INT module is disabled. The INT module is however capable of
waking-up the CPU from wait mode if an interrupt occurs. Please refer to
from Stop or Wait Mode”
Stop Mode
In stop mode, the clock to the INT module is disabled. The INT module is however capable of
waking-up the CPU from stop mode if an interrupt occurs. Please refer to
from Stop or Wait Mode”
Freeze mode (BDM active)
In freeze mode (BDM active), the interrupt vector base register is overridden internally. Please
refer to
shows a block diagram of the INT module.
Modes of Operation
Block Diagram
Section 7.3.1.1, “Interrupt Vector Base Register (IVBR)”
MC9S12VR Family Reference Manual,
Preliminary - Subject to Change Without Notice
for details.
for details.
Rev. 2.2
for details.
Section 7.5.3, “Wake Up
Section 7.5.3, “Wake Up
Freescale Semiconductor