mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 289

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Read: Anytime
Write: Anytime
Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
Freescale Semiconductor
Module Base + 0x00006
PCLKAB7
PCLKAB6
PCLKAB5
PCLKAB4
PCLKAB3
PCLKAB2
PCLKAB1
PCLKAB0
Reset
Field
unavailable bits return a zero
7
6
5
4
3
2
1
0
W
R
PCLKAB7
Pulse Width Channel 7 Clock A/B Select
0 Clock B or SB is the clock source for PWM channel 7, as shown in
1 Clock A or SA is the clock source for PWM channel 7, as shown in
Pulse Width Channel 6 Clock A/B Select
0 Clock B or SB is the clock source for PWM channel 6, as shown in
1 Clock A or SA is the clock source for PWM channel 6, as shown in
Pulse Width Channel 5 Clock A/B Select
0 Clock A or SA is the clock source for PWM channel 5, as shown in
1 Clock B or SB is the clock source for PWM channel 5, as shown in
Pulse Width Channel 4 Clock A/B Select
0 Clock A or SA is the clock source for PWM channel 4, as shown in
1 Clock B or SB is the clock source for PWM channel 4, as shown in
Pulse Width Channel 3 Clock A/B Select
0 Clock B or SB is the clock source for PWM channel 3, as shown in
1 Clock A or SA is the clock source for PWM channel 3, as shown in
Pulse Width Channel 2 Clock A/B Select
0 Clock B or SB is the clock source for PWM channel 2, as shown in
1 Clock A or SA is the clock source for PWM channel 2, as shown in
Pulse Width Channel 1 Clock A/B Select
0 Clock A or SA is the clock source for PWM channel 1, as shown in
1 Clock B or SB is the clock source for PWM channel 1, as shown in
Pulse Width Channel 0 Clock A/B Select
0 Clock A or SA is the clock source for PWM channel 0, as shown in
1 Clock B or SB is the clock source for PWM channel 0, as shown in
0
7
Register bits PCLKAB0 to PCLKAB7 can be written anytime. If a clock
select is changed while a PWM signal is being generated, a truncated or
stretched pulse can occur during the transition.
PCLKAB6
0
6
Figure 9-9. PWM Clock Select Register (PWMCLK)
MC9S12VR Family Reference Manual, Rev. 2.2
Table 9-11. PWMCLK Field Descriptions
Preliminary - Subject to Change Without Notice
PCLKAB5
0
5
PCLKAB4
NOTE
0
4
Description
PCLKAB3
0
3
PCLKAB2
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Pulse-Width Modulator (S12PWM8B8CV2)
0
2
9-6.
9-6.
9-6.
9-6.
9-5.
9-5.
9-5.
9-5.
9-6.
9-6.
9-6.
9-6.
9-5.
9-5.
9-5.
9-5.
PCLKAB1
0
1
PCLKAB0
0
0
289