mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 430

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mc9s12vr48

Manufacturer Part Number
mc9s12vr48
Description
S12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
LIN Physical Layer (S12LINPHYV1)
15.3.2
This section describes all the LIN Physical Layer registers and their individual bits.
15.3.2.1
1
430
Module Base + Address 0x0000
Read: Anytime
Write: Anytime
Reset
LPDR1
LPDR0
Field
1
0
W
R
Register Descriptions
Port LP Data Bit 1
The LIN Physical Layer LPTXD input (see
of the LPTXD input is done in PIM Module, see PIM Block guide for more info.
Port LP Data Bit 0
Read-only bit. The LIN Physical Layer LPRXD output state can be read at any time.
Port LP Data Register (LPDR)
0
0
7
= Unimplemented
0
0
6
Figure 15-2. Port LP Data Register (LPDR)
MC9S12VR Family Reference Manual,
Preliminary - Subject to Change Without Notice
Table 15-4. LPDR Fields Description
0
0
5
Figure
0
0
4
15-1) can be directly controlled by this register bit. The routing
Description
0
0
3
Rev. 2.2
0
0
2
Access: User read/write
LPDR1
Freescale Semiconductor
1
1
LPDR0
1
0
1

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