mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 96

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Port Integration Module (S12VRPIMV2)
2.4.4.1
The XIRQ pin allows requesting non-maskable interrupts after reset initialization. During reset, the X bit
in the condition code register is set and any interrupts are masked until software enables them.
The IRQ pin allows requesting asynchronous interrupts. The interrupt input is disabled out of reset. To
enable the interrupt the IRQCR[IRQEN] bit must be set and the I bit cleared in the condition code register.
The interrupt can be configured for level-sensitive or falling-edge-sensitive triggering. If IRQCR[IRQEN]
is cleared while an interrupt is pending, the request will deassert.
Both interrupts are capable to wake-up the device from stop mode. Means for glitch filtering are not
provided on these pins.
2.4.4.2
Ports P, L and AD offer pin interrupt capability. The related interrupt enable (PIE) as well as the sensitivity
to rising or falling edges (PPS) can be individually configured on per-pin basis. All bits/pins in a port share
the same interrupt vector. Interrupts can be used with the pins configured as inputs or outputs.
An interrupt is generated when a bit in the port interrupt flag (PIF) and its corresponding port interrupt
enable (PIE) are both set. The pin interrupt feature is also capable to wake up the CPU when it is in stop
or wait mode.
A digital filter on each pin prevents short pulses from generating an interrupt. A valid edge on an input is
detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active
level. Else the sampling logic is restarted.
In run and wait mode the filters are continuously clocked by the bus clock. Pulses with a duration of t
< n
a pin interrupt.
In stop mode the clock is generated by an RC-oscillator. The minimum pulse length varies over process
conditions, temperature and voltage
assuredly filtered out while pulses with a duration of t
Please refer to the appendix table “Pin Interrupt Characteristics” for pulse length limits.
To maximize current saving the RC oscillator is active only if the following condition is true on any
individual pin:
Sample count <= 4 (at active or passive level) and interrupt enabled (PIE[x]=1) and interrupt flag not set
(PIF[x]=0).
96
P_MASK
/f
bus
XIRQ, IRQ Interrupts
Pin Interrupts and Wakeup
are assuredly filtered out while pulses with a duration of t
Port L pin interrupt
Port AD pin interrupt
Port P over-current
Module Interrupt Sources
MC9S12VR Family Reference Manual,
Preliminary - Subject to Change Without Notice
Table 2-50. PIM Interrupt Sources
(Figure
2-47). Pulses with a duration of t
PIEL[PIEL3-PIEL0]
PIE1AD[PIE1AD5-PIE1AD0]
PIEP[OCIE]
PULSE
Local Enable
> t
P_PASS
Rev. 2.2
guarantee a wakeup event.
PULSE
PULSE
> n
P_PASS
< t
Freescale Semiconductor
P_MASK
/f
bus
guarantee
are
PULSE