mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 172

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mc9s12vr48

Manufacturer Part Number
mc9s12vr48
Description
S12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Clock, Reset and Power Management (S12CPMU_UHV)
4.6
The interrupt/reset vectors requested by the S12CPMU_UHV are listed in
specification for related vector addresses and priorities.
4.6.1
4.6.1.1
The clock source for the RTI is either IRCCLK or OSCCLK depending on the setting of the RTIOSCSEL
bit. In Stop Mode with PSTP=1 (Pseudo Stop Mode), RTIOSCSEL=1 and PRE=1 the RTI continues to
run, else the RTI counter halts in Stop Mode.
The RTI can be used to generate hardware interrupts at a fixed periodic rate. If enabled (by setting
RTIE=1), this interrupt will occur at the rate selected by the CPMURTI register. At the end of the RTI
time-out period the RTIF flag is set to one and a new RTI time-out period starts immediately.
A write to the CPMURTI register restarts the RTI time-out period.
4.6.1.2
The S12CPMU_UHV generates a PLL Lock interrupt when the lock condition (LOCK status bit) of the
PLL changes, either from a locked state to an unlocked state or vice versa. Lock interrupts are locally
disabled by setting the LOCKIE bit to zero. The PLL Lock interrupt flag (LOCKIF) is set to1 when the
lock condition has changed, and is cleared to 0 by writing a 1 to the LOCKIF bit.
4.6.1.3
When the OSCE bit is 0, then UPOSC stays 0. When OSCE=1 the UPOSC bit is set after the LOCK bit is
set.
172
Interrupts
Description of Interrupt Operation
Real Time Interrupt (RTI)
PLL Lock Interrupt
Oscillator Status Interrupt
RTI time-out interrupt
Low voltage interrupt
Interrupt Source
Periodical Interrupt
PLL lock interrupt
High temperature
Oscillator status
Autonomous
Table 4-32. S12CPMU_UHV Interrupt Vectors
interrupt
interrupt
MC9S12VR Family Reference Manual,
Preliminary - Subject to Change Without Notice
Mask
CCR
I bit
I bit
I bit
I bit
I bit
I bit
CPMUAPICTL (APIE)
CPMUHTCTL (HTIE)
CPMUINT (LOCKIE)
CPMULVCTL (LVIE)
CPMUINT (OSCIE)
CPMUINT (RTIE)
Local Enable
Rev. 2.2
Table
4-32. Refer to MCU
Freescale Semiconductor

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