mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 173

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Upon detection of a status change (UPOSC) the OSCIF flag is set. Going into Full Stop Mode or disabling
the oscillator can also cause a status change of UPOSC.
Any change in PLL configuration or any other event which causes the PLL lock status to be cleared leads
to a loss of the oscillator status information as well (UPOSC=0).
Oscillator status change interrupts are locally enabled with the OSCIE bit.
4.6.1.4
In FPM the input voltage VDDA is monitored. Whenever VDDA drops below level V
LVDS is set to 1. When VDDA rises above level V
indicated by flag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable bit LVIE
= 1.
4.6.1.5
In FPM the junction temperature T
is set to 1. Vice versa, HTDS is reset to 0 when T
HTIF = 1, is triggered by any change of the status bit HTDS, if interrupt enable bit HTIE = 1.
4.6.1.6
The API sub-block can generate periodical interrupts independent of the clock source of the MCU. To
enable the timer, the bit APIFE needs to be set.
The API timer is either clocked by the Autonomous Clock (ACLK - trimmable internal RC oscillator) or
the Bus Clock. Timer operation will freeze when MCU clock source is selected and Bus Clock is turned
off. The clock source can be selected with bit APICLK. APICLK can only be written when APIFE is not
set.
The APIR[15:0] bits determine the interrupt period. APIR[15:0] can only be written when APIFE is
cleared. As soon as APIFE is set, the timer starts running for the period selected by APIR[15:0] bits. When
the configured time has elapsed, the flag APIF is set. An interrupt, indicated by flag APIF = 1, is triggered
if interrupt enable bit APIE = 1. The timer is re-started automatically again after it has set APIF.
The procedure to change APICLK or APIR[15:0] is first to clear APIFE, then write to APICLK or
APIR[15:0], and afterwards set APIFE.
The API Trimming bits APITR[5:0] must be set so the minimum period equals 0.2 ms if stable frequency
is desired.
See
1. For details please refer to “4.4.6 System Clock Configurations”
Freescale Semiconductor
Table 4-19
Low-Voltage Interrupt (LVI)
HTI - High Temperature Interrupt
Autonomous Periodical Interrupt (API)
Loosing the oscillator status (UPOSC=0) affects the clock configuration of
the system
for the trimming effect of APITR.
1
. This needs to be dealt with in application software.
MC9S12VR Family Reference Manual, Rev. 2.2
Preliminary - Subject to Change Without Notice
J
is monitored. Whenever T
NOTE
J
get below level T
LVID
the status bit LVDS is cleared to 0. An interrupt,
Clock, Reset and Power Management (S12CPMU_UHV)
J
exceeds level T
HTID
. An interrupt, indicated by flag
HTIA
the status bit HTDS
LVIA,
the status bit
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