mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 164

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Clock, Reset and Power Management (S12CPMU_UHV)
4.4.2
An example for startup of the clock system from Reset is given in
4.4.3
An example of what happens going into Stop Mode and exiting Stop Mode after an interrupt is shown in
Figure
Depending on the COP configuration there might be an additional significant latency time until COP is
active again after exit from Stop Mode due to clock domain crossing synchronization. This latency time
of 2 ACLK cycles occurs if COP clock source is ACLK and the CSAD bit is set and must be added to the
device Stop Mode recovery time t
164
LOCK
System
Reset
LOCK
SYNDIV
POSTDIV $03 (default target f
CPU
PLLCLK
PLLCLK
CPU
4-34. Disable PLL Lock interrupt (LOCKIE=0) before going into Stop Mode.
execution
f
PLLRST
Startup from Reset
Stop Mode using PLLCLK as Bus Clock
$18 (default target f
reset state
768 cycles
) (
STOP instruction
Figure 4-34. Stop Mode using PLLCLK as Bus Clock
wakeup
Figure 4-33. Startup of clock system after Reset
VCO
PLL
MC9S12VR Family Reference Manual,
Preliminary - Subject to Change Without Notice
STP_REC
=f
vector fetch, program execution
=50MHz)
VCO
/4 = 12.5MHz)
t
. After exit from Stop Mode (Pseudo, Full) for this latency time
STP_REC
f
PLL
increasing
t
lock
interrupt
t
lock
continue execution
Figure
Rev. 2.2
f
PLL
=16MHz
4-33.
example change
of POSTDIV
$01
Freescale Semiconductor
f
PLL
=32 MHz