mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 69

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

1
2.3.19
Freescale Semiconductor
Address 0x024A
Read: Anytime
Write: Anytime
DDRS
DDRS
DDRS
DDRS
Field
Reset
5
4
3
2
W
R
Data Direction Register port S —
This bit determines whether the associated pin is an input or output. Depending on the configuration of the enabled
SPI the I/O state will be forced to be input or output. In this case the data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
Data Direction Register port S —
This bit determines whether the associated pin is an input or output. Depending on the configuration of the enabled
SPI the I/O state will be forced to be input or output. In this case the data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
Data Direction Register port S —
This bit determines whether the associated pin is an input or output. The ECLK output function, routed SCI1 and
routed PWM function forces the I/O state to output if enabled. Depending on the configuration of the enabled SPI
the I/O state will be forced to be input or output. In these cases the data direction bit will not change. The routed
ETRIG function has no effect on the I/O state.
1 Associated pin is configured as output
0 Associated pin is configured as input
Data Direction Register port S —
This bit determines whether the associated pin is an input or output. Depending on the configuration of the enabled
SPI the I/O state will be forced to be input or output. The routed SCI1 function forces the I/O state to input if enabled.
The routed PWM function forces the I/O state to output if enabled. In these cases the data direction bit will not
change. The routed ETRIG function has no effect on the I/O state.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port S Data Direction Register (DDRS)
0
0
7
0
0
6
Figure 2-17. Port S Data Direction Register (DDRS)
Table 2-19. DDRS Register Field Descriptions
MC9S12VR Family Reference Manual, Rev. 2.2
Preliminary - Subject to Change Without Notice
DDRS5
5
0
DDRS4
0
4
Description
DDRS3
0
3
DDRS2
Port Integration Module (S12VRPIMV2)
0
2
DDRS1
Access: User read/write
0
1
DDRS0
0
0
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