mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 43

no-image

mc9s12vr48

Manufacturer Part Number
mc9s12vr48
Description
S12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.11.2
Table 1-10
Chapter 7, “Interrupt Module
the vectors.
Freescale Semiconductor
Vector base + $EC
Vector base + $DA
Vector base + $CE
Vector base + $E0
Vector base + $D8
Vector base + $D4
Vector base + $D2
Vector base + $D0
Vector base + $F8
Vector base+ $DE
Vector base+ $DC
Vector base+ $EE
Vector base+ $EA
Vector base+ $D6
Vector Address
Vector base+ $F6
Vector base+ $F4
Vector base+ $F2
Vector base+ $F0
Vector base+ $E8
Vector base+ $E6
to
to
Vector Address
lists all interrupt sources and vectors in the default order of priority. The interrupt module (see
Interrupt Vectors
$FFFA
1
Unimplemented instruction trap
RTI time-out interrupt
TIM timer channel 0
TIM timer channel 1
TIM timer channel 2
TIM timer channel 3
Table 1-10. Interrupt Vector Locations (Sheet 1 of 2)
TIM timer overflow
Interrupt Source
(S12SINTV1)”) provides an interrupt vector base register (IVBR) to relocate
MC9S12VR Family Reference Manual, Rev. 2.2
Port L
XIRQ
SCI0
SCI1
ADC
SWI
IRQ
Preliminary - Subject to Change Without Notice
SPI
COP watchdog reset
Reset Source
Mask
None
None
CCR
X Bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
Reserved
Reserved
Reserved
SPICR1 (SPIE, SPTIE)
(TIE, TCIE, RIE, ILIE)
(TIE, TCIE, RIE, ILIE)
PIEL (PIEL3-PIEL0)
ATDCTL2 (ASCIE)
CPMUINT (RTIE)
Mask
None
IRQCR (IRQEN)
CCR
Local Enable
TSCR2(TOF)
SCI0CR2
SCI1CR2
TIE (C0I)
TIE (C1I)
TIE (C2I)
TIE (C3I)
None
None
None
CR[2:0] in CPMUCOP register
Device Overview MC9S12VR-Family
Local Enable
from STOP
Wake up
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
4.6 Interrupts
-
-
from WAIT
Wake up
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
-
43

Related parts for mc9s12vr48