mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 81

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

1
1
1
Address 0x0269
2.3.32
2.3.33
Freescale Semiconductor
Address 0x26A
1
Refer to PTTEL bit description in
Read: Anytime
Write: No Write
Read: Anytime
Write: Anytime
DIENL
Field
Reset
Reset
Refer to PTTEL bit description in
3-0
Field
PTIL
W
W
3-0
R
R
Digital Input ENable port L — Input buffer control
This bit controls the HVI digital input function. If set to 1 the input buffers are enabled and the pin can be used with
the digital function. If the analog input function is enabled (PTAL[PTAENL]=1) the input buffer of the selected HVI pin
is forced off
1 Associated pin digital input is enabled if not used as analog input in run mode
0 Associated pin digital input is disabled
Port L Input Register (PTIL)
Port L Digital Input Enable Register (DIENL)
0
0
0
0
7
7
PorT Input data register port L —
A read returns the synchronized input state if the associated pin is used in digital mode, that is the related
DIENL bit is set to 1 and the pin is not used in analog mode (PTAL[PTAENL]=1). See
Analog Access Register
1
in run mode and is released to be active in stop mode only if DIENL=1.
Figure 2-32. Port L Digital Input Enable Register (DIENL)
0
0
0
0
6
6
Section 2.3.34, “Port L Analog Access Register (PTAL)
Table 2-34. DIENL Register Field Descriptions
Table 2-33. PTIL - Register Field Descriptions
Section 2.3.34, “Port L Analog Access Register (PTAL)
MC9S12VR Family Reference Manual, Rev. 2.2
Figure 2-31. Port L Input Register (PTIL)
Preliminary - Subject to Change Without Notice
(PTAL)”. A one is read in any other case
5
0
0
5
0
0
1
0
0
0
0
4
4
Description
Description
DIENL3
PTIL3
0
0
3
3
1
.
DIENL2
PTIL2
Port Integration Module (S12VRPIMV2)
0
0
2
2
for an override condition.
1
for an override condition.
DIENL1
Section 2.3.34, “Port L
Access: User read/write
PTIL1
Access: User read only
0
0
1
1
DIENL0
PTIL0
0
0
0
0
81
1
1