mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 168

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Clock, Reset and Power Management (S12CPMU_UHV)
4.4.6.3
In this mode, the Bus Clock is based on the external oscillator clock. The reference clock for the PLL is
based on the external oscillator.
The clock sources for COP and RTI can be based on the internal reference clock generator or on the
external oscillator clock or the RC-Oscillator (ACLK).
This mode can be entered from default mode PEI by performing the following steps:
Loosing PLL lock status (LOCK=0) means loosing the oscillator status information as well (UPOSC=0).
The impact of loosing the oscillator status (UPOSC=0) in PBE mode is as follows:
Application software needs to be prepared to deal with the impact of loosing the oscillator status at any
time.
4.5
4.5.1
All reset sources are listed in
priorities.
4.5.2
Upon detection of any reset of
cycles. After 512 PLLCLK cycles the RESET pin is released. The reset generator of the S12CPMU_UHV
168
1. Make sure the PLL configuration is valid.
2. Enable the external Oscillator (OSCE bit)
3. Wait for the oscillator to start-up and the PLL being locked (LOCK = 1) and (UPOSC =1)
4. Clear all flags in the CPMUFLG register to be able to detect any status bit change.
5. Optionally status interrupts can be enabled (CPMUINT register).
6. Select the Oscillator clock as Bus clock (PLLSEL=0)
•
•
PLLSEL is set automatically and the Bus clock is switched back to the PLL clock.
The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the
PLL locks again.
Resets
General
Description of Reset Operation
PLL Bypassed External Mode (PBE)
Low Voltage Reset (LVR)
Power-On Reset (POR)
Illegal Address Reset
Clock Monitor Reset
External pin RESET
Reset Source
COP Reset
Table
Table
MC9S12VR Family Reference Manual,
Preliminary - Subject to Change Without Notice
4-29. Refer to MCU specification for related vector addresses and
4-29, an internal circuit drives the RESET pin low for 512 PLLCLK
Table 4-29. Reset Summary
OSCE Bit in CPMUOSC register
CR[2:0] in CPMUCOP register
Local Enable
Rev. 2.2
None
None
None
None
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