mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 332

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mc9s12vr48

Manufacturer Part Number
mc9s12vr48
Description
S12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Serial Communication Interface (S12SCIV5)
10.4.6
10.4.6.1
The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI
control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in
SCI data register high (SCIDRH) is the ninth bit (bit 8).
10.4.6.2
During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data register
is the read-only buffer between the internal data bus and the receive shift register.
After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the
SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set,
332
From TXD Pin
or Transmitter
SCRXD
LOOPS
RSRC
Receiver
Receiver Character Length
Character Reception
RXPOL
Control
SBR12:SBR0
Loop
Clock
Bus
Baud Divider
Figure 10-20. SCI Receiver Block Diagram
WAKE
MC9S12VR Family Reference Manual,
Preliminary - Subject to Change Without Notice
RAF
RE
ILT
PE
PT
M
Recovery
Detect Logic
Data
Detect Logic
Active Edge
Break
BRKDFE
Checking
Wakeup
Parity
Logic
Internal Bus
H
RXEDGIE
RXEDGIF
Rev. 2.2
BRKDIF
BRKDIE
8
11-Bit Receive Shift Register
RDRF
OR
7
SCI Data Register
6
5
4
NF
PE
FE
3
R8
IDLE
Freescale Semiconductor
ILIE
RIE
2
Break IRQ
RX Active Edge IRQ
1
0
L
RWU
RDRF/OR
Idle IRQ
IRQ

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