mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 83

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mc9s12vr48

Manufacturer Part Number
mc9s12vr48
Description
S12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Freescale Semiconductor
PTAENL
Field
PTAL
1-0
3
PorT ADC connection ENable port L —
This bit enables the analog signal link of an HVI pin selected by PTAL[1:0] to an ADC channel. If set to 1 the analog
input function takes precedence over the digital input in run mode by forcing off the input buffers if not overridden by
PTTEL=1.
1 Selected pin by PTAL[1:0] is connected to ADC channel
0 No Port L pin is connected to ADC
PorT ADC connection selector port L —
These selector bits choose the HVI pin connecting to an ADC channel if enabled (PTAENL=1). Refer to
for details.
When enabling the resistor paths to ground by setting PTAL[PTAENL]=1
or by changing PTAL[PTAL1:PTAL0], a settling time of t
bus cycles must be considered to let internal nodes be loaded with correct
values.
Table 2-35. PTAL Register Field Descriptions (continued)
1
PTAL[PTAL1]
Table 2-36. HVI pin connected to ADC channel
Refer to device overview section for channel assignment
MC9S12VR Family Reference Manual, Rev. 2.2
Preliminary - Subject to Change Without Notice
0
0
1
1
PTAL[PTAL0]
NOTE
0
1
0
1
Description
HVI pin connected
to ADC
HVI0
HVI1
HVI2
HVI3
1
UNC_HVI
Port Integration Module (S12VRPIMV2)
+ two
Table 2-36
83

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