mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 34

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Device Overview MC9S12VR-Family
1.7.2.15.4
This signal is associated with the MOSI functionality of the serial peripheral interface SPI. This signal acts
as master output during master mode or as slave input during slave mode
1.7.2.16
1.7.2.16.1
This signal is the LINPHY transmit input. See Figure 2-22
1.7.2.16.2
This signal is the LINPHY receive output. See Figure 2-22
1.7.2.17
1.7.2.17.1
Those signals are associated with the receive functionality of the serial communication interfaces SCI1-0.
1.7.2.17.2
Those signals are associated with the transmit functionality of the serial communication interfaces SCI1-0.
1.7.2.18
The signals PWM[7:0] are associated with the PWM module outputs.
1.7.2.19
1.7.2.19.1
This signal is associated with the output of the divided bus clock (ECLK).
1.7.2.20
These signals are inputs to the Analog-to-Digital Converter. Their purpose is to trigger ADC conversions.
1.7.2.21
The signals IOC[3:0] are associated with the input capture or output compare functionality of the timer
(TIM) module.
34
LINPHY Signals
SCI Signals
PWM[7:0] Signals
Internal Clock outputs
ETRIG[1:0]
IOC[3:0] Signals
MOSI Signal
LPTXD Signal
LPRXD Signal
RXD[1:0] Signals
TXD[1:0] Signals
ECLK
This feature is only intended for debug purposes at room temperature.
It must not be used for clocking external devices in an application.
MC9S12VR Family Reference Manual,
Preliminary - Subject to Change Without Notice
NOTE
Rev. 2.2
Freescale Semiconductor