mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 165

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

of 2 ACLK cycles no Stop Mode request (STOP instruction) should be generated to make sure the COP
counter can increment at each Stop Mode exit.
4.4.4
An example of what happens going into Full Stop Mode and exiting Full Stop Mode after an interrupt is
shown in
Disable PLL Lock interrupt (LOCKIE=0) and oscillator status change interrupt (OSCIE=0) before going
into Full Stop Mode.
Depending on the COP configuration there might be a significant latency time until COP is active again
after exit from Stop Mode due to clock domain crossing synchronization. This latency time of 2 ACLK
cycles occurs if COP clock source is ACLK and the CSAD bit is set and must be added to the device Stop
Mode recovery time t
cycles no Stop Mode request (STOP instruction) should be generated to make sure the COP counter can
increment at each Stop Mode exit.
Freescale Semiconductor
Core
Clock
PLLCLK
OSCCLK
PLLSEL
UPOSC
CPU
execution
Figure
Full Stop Mode using Oscillator Clock as Bus Clock
4-35.
Figure 4-35. Full Stop Mode using Oscillator Clock as Bus Clock
STP_REC
STOP instruction
wakeup
automatically set when going into Full Stop Mode
. After exit from Stop Mode (Pseudo, Full) for this latency time of 2 ACLK
MC9S12VR Family Reference Manual, Rev. 2.2
Preliminary - Subject to Change Without Notice
t
STP_REC
select OSCCLK as Core/Bus Clock by writing PLLSEL to “0”
interrupt
t
Clock, Reset and Power Management (S12CPMU_UHV)
lock
continue execution
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