mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 131

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

4.3.2.3
The POSTDIV register controls the frequency ratio between the VCOCLK and the PLLCLK.
Read: Anytime
Write: If PLLSEL=1 write anytime, else write has no effect
4.3.2.4
This register provides S12CPMU_UHV status bits and flags.
Read: Anytime
Write: Refer to each bit for individual write conditions
Freescale Semiconductor
1. PORF is set to 1 when a power on reset occurs. Unaffected by System Reset.
2. LVRF is set to 1 when a low voltage reset occurs. Unaffected by System Reset. Set by power on reset.
3. ILAF is set to 1 when an illegal address reset occurs. Unaffected by System Reset. Cleared by power on reset.
0x0036
0x0037
Reset
Reset
If PLL is selected (PLLSEL=1)
If PLL is locked (LOCK=1)
If PLL is not locked (LOCK=0)
W
W
R
R
RTIF
S12CPMU_UHV Post Divider Register (CPMUPOSTDIV)
S12CPMU_UHV Flags Register (CPMUFLG)
0
0
0
7
7
Figure 4-6. S12CPMU_UHV Post Divider Register (CPMUPOSTDIV)
= Unimplemented or Reserved
= Unimplemented or Reserved
Note 1
PORF
Figure 4-7. S12CPMU_UHV Flags Register (CPMUFLG)
0
0
6
6
MC9S12VR Family Reference Manual, Rev. 2.2
Preliminary - Subject to Change Without Notice
f PLL
f PLL
f bus
Note 2
LVRF
0
0
5
5
=
=
=
f PLL
------------ -
---------------------------------------- -
(
f VCO
---------------
POSTDIV
2
4
f VCO
LOCKIF
0
0
4
4
+
1
)
LOCK
Clock, Reset and Power Management (S12CPMU_UHV)
0
0
3
3
POSTDIV[4:0]
Note 3
ILAF
0
2
2
OSCIF
1
0
1
1
UPOSC
1
0
0
0
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