mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 285

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
The clock source of each PWM channel is determined by PCLKx bits in PWMCLK and PCLKABx bits
in PWMCLKAB (see
0, 1, 4, 5, the selection is shown in
9.3.2.4
This register selects the prescale clock source for clocks A and B independently.
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x0003
PCLK[7:0]
Reset
Field
7-0
unavailable bits return a zero
W
R
Pulse Width Channel 7-0 Clock Select
0 Clock A or B is the clock source for PWM channel 7-0, as shown in
1 Clock SA or SB is the clock source for PWM channel 7-0, as shown in
PWM Prescale Clock Select Register (PWMPRCLK)
0
0
7
PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock
pre-scale is changed while a PWM signal is being generated, a truncated or
stretched pulse can occur during the transition.
PCLKAB[2,3,6,7]
PCLKAB[0,1,4,5]
= Unimplemented or Reserved
Figure 9-6. PWM Prescale Clock Select Register (PWMPRCLK)
Section 9.3.2.7, “PWM Clock A/B Select Register
PCKB2
Table 9-5. PWM Channel 0, 1, 4, 5 Clock Source Selection
Table 9-6. PWM Channel 2, 3, 6, 7 Clock Source Selection
0
6
0
0
1
1
0
0
1
1
MC9S12VR Family Reference Manual, Rev. 2.2
Preliminary - Subject to Change Without Notice
Table 9-4. PWMCLK Field Descriptions
Table
PCKB1
0
5
PCLK[0,1,4,5]
PCLK[2,3,6,7]
9-5; For Channel 2, 3, 6, 7, the selection is shown in
0
1
0
1
0
1
0
1
PCKB0
NOTE
0
4
Description
Clock Source Selection
Clock Source Selection
0
0
3
Clock SA
Clock SB
Clock SB
Clock SA
Clock A
Clock B
Clock B
Clock A
Table 9-5
PCKA2
Pulse-Width Modulator (S12PWM8B8CV2)
(PWMCLKAB)). For Channel
Table 9-5
0
2
and
and
Table
PCKA1
Table
0
1
9-6.
9-6.
Table
PCKA0
0
0
9-6.
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