mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 134

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mc9s12vr48

Manufacturer Part Number
mc9s12vr48
Description
S12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Clock, Reset and Power Management (S12CPMU_UHV)
4.3.2.6
This register controls S12CPMU_UHV clock selection.
Read: Anytime
Write:
134
0x0039
Reset
5. Only possible if PROT=0 (CPMUPROT register) in all MCU Modes (Normal and Special Mode).
6. All bits in Special Mode (if PROT=0).
7. PLLSEL, PSTP, PRE, PCE, RTIOSCSEL: In Normal Mode (if PROT=0).
8. CSAD: In Normal Mode (if PROT=0) until CPMUCOP write once has taken place.
9. COPOSCSEL0: In Normal Mode (if PROT=0) until CPMUCOP write once has taken place.
10. COPOSCSEL1: In Normal Mode (if PROT=0) until CPMUCOP write once has taken place.
W
R
If COPOSCSEL0 was cleared by UPOSC=0 (entering Full Stop Mode with COPOSCSEL0=1 or
insufficient OSCCLK quality), then COPOSCSEL0 can be set once again.
PLLSEL
COPOSCSEL1 will not be cleared by UPOSC=0 (entering Full Stop Mode with
COPOSCSEL1=1 or insufficient OSCCLK quality if OSCCLK is used as clock source for
other clock domains: for instance core clock etc.).
S12CPMU_UHV Clock Select Register (CPMUCLKS)
1
7
After writing CPMUCLKS register, it is strongly recommended to read
back CPMUCLKS register to make sure that write of PLLSEL,
RTIOSCSEL and COPOSCSEL was successful.
= Unimplemented or Reserved
Figure 4-9. S12CPMU_UHV Clock Select Register (CPMUCLKS)
PSTP
0
6
MC9S12VR Family Reference Manual,
Preliminary - Subject to Change Without Notice
CSAD
0
5
OSCSEL1
COP
NOTE
0
4
PRE
0
3
Rev. 2.2
PCE
0
2
OSCSEL
Freescale Semiconductor
RTI
0
1
OSCSEL0
COP
0
0

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