mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 94

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Port Integration Module (S12VRPIMV2)
Voltages up to V
to logic level. There are two modes, digital and analog, where these signals can be processed.
2.4.3.6.1
In digital mode the input buffers are enabled (DIENL[x]=1 & PTAL[PTAENL]=0). The synchronized pin
input state determined at threshold level V
set on input transitions if enabled (PIEL[x]=1) and configured for the related edge polarity (PPSL).
Wakeup from stop mode is supported.
2.4.3.6.2
In analog mode (PTAL[PTAENL]=1) the voltage applied to a selectable pin (PTAL[PTAL1:PTAL0]) can
be measured on an internal ADC channel (refer to device overview section for channel assignment). One
of two input divider ratios (Ratio
94
V
PIRL[x]
HVI
ANALOG[x]
& STOP
& PTADIRL
R
EXT_HVI
10K
Digital Mode Operation
Analog Mode Operation
500K
110K
440K
HVIx
40K
can be applied to all HVI pins. Internal voltage dividers scale the input signals down
HVIx
ANALOG[x]
& PTTEL
& PTPSL
& STOP
MC9S12VR Family Reference Manual,
H_HVI
Preliminary - Subject to Change Without Notice
VDDX
Figure 2-46. HVI Block Diagram
, Ratio
TH_HVI
ANALOG[x]
& STOP & PTADIRL
ANALOG[x]
& STOP & PTADIRL
L_HVI
ANALOG[x] = PTAENL & PTAL[1:0]
(DIENL[x] & (ANALOG[x] | STOP))
| (ANALOG[x] & PTADIRL & PTTEL & STOP)
can be read in register PTIL. Interrupt flags (PIFL) are
) can be chosen on each analog input (PIRL[x]) or the
(other inputs)
Rev. 2.2
Freescale Semiconductor
Impedance
Converter
Input Buffer
PTAENL
& PTADIRL
& PTABYPL
PTIL[x]
ADC