mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 169

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

waits for additional 256PLLCLK cycles and then samples the RESET pin to determine the originating
source.
The internal reset of the MCU remains asserted while the reset generator completes the 768 PLLCLK
cycles long reset sequence. In case the RESET pin is externally driven low for more than these 768
PLLCLK cycles (External Reset), the internal reset remains asserted longer.
4.5.2.1
If the external oscillator is enabled (OSCE=1) in case of loss of oscillation or the oscillator frequency is
below the failure assert frequency f
Freescale Semiconductor
Table 4-30
Sampled RESET Pin
(256 cycles after
Clock Monitor Reset
While System Reset is asserted the PLLCLK runs with the frequency
f
PLLCLK
VCORST
RESET
release)
shows which vector will be fetched.
1
1
1
0
.
MC9S12VR Family Reference Manual, Rev. 2.2
Oscillator monitor
Preliminary - Subject to Change Without Notice
fail pending
CMFA
Table 4-30. Reset Vector Selection
Figure 4-37. RESET Timing
X
0
1
0
(see device electrical characteristics for values), the
S12_CPMU drives
RESET pin low
512 cycles
NOTE
time-out
pending
)
COP
(
X
X
f
0
1
VCORST
Clock, Reset and Power Management (S12CPMU_UHV)
S12_CPMU releases
RESET pin
256 cycles
f
VCORST
Illegal Address Reset
Illegal Address Reset
Clock Monitor Reset
External pin RESET
External pin RESET
)
(
Vector Fetch
COP Reset
POR
POR
possibly
RESET
driven low
externally
LVR
LVR
)
(
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